1. Field of the Invention
The present invention generally relates to pulse width modulated (PWM) inverters for converting direct current to alternating current and, more particularly, to an enhanced real-time control of PWM inverters which accounts for link and load variation by vernier positioning of all switching events.
2. Description of the Prior Art
PWM inverters are employed to convert direct current (d.c.) to alternating current (a.c.). In many applications, it is important to carefully regulate the quality of the a.c. signal generated by the inverter, i.e., minimize distortions of the a.c. waveform. Accordingly, it is customary to define a point of regulation (POR) downstream of the inverter at which the voltage and current of the a.c. signal generated by the inverter is sampled. The sampled voltage and current is used to select appropriate PWM switching patterns to minimize distortion at the POR. Based on the voltage and current sensed at the POR, an inverter controller selects, or creates in real time, an appropriate PWM pattern to minimize the distortion at the POR. As changes in real and reactive component of the power factor of electrical loads coupled to the inverter and changes in the balance in loads in a three-phase system may distort the a.c. waveform; the PWM patterns fed to the inverter change to minimize distortions of the waveform.
A PWM pattern comprises a set of switching events that chop a d.c. voltage in an inverter to produce pulses which, when filtered, approximates a sinusoidal a.c. signal. The pulses are created by a PWM pattern are of varying width. Normally, the switches adequately reproduce the desired PWM pattern and thereby create an accurate approximation of a sinusoidal a.c. signal from the d.c. voltage. Prior art patterns assume a ripple-free (i.e., stiff) d.c. input link. However, under some actual load conditions (particularly when loads are unbalanced), ripple is present on the d.c. link and causes a distortion in the inverter output pulse pattern from that desired and a consequential distortion of the filtered waveform.
The desirability of reducing the harmonic content of an inverter circuit output is recognized in U.S. Pat. No. 4,382,275 to Glennon which relates to a pulse width modulated inverter circuit having an output circuit with reduced harmonic content. The inverter circuit includes a first circuit that provides a filtered fundamental pulse width modulated signal. A second circuit is electrically coupled to the first circuit to receive the signal and sum therewith a controlled signal and the filtered fundamental pulse width modulated signal. The second circuit thereby provides the output signal with reduced harmonic content.
Another patent to Glennon, U.S. Pat. No. 4,519,022, discloses a ripple reduction circuit for an inverter which converts d.c. power supplied on d.c. buses into a.c. power to drive a load that includes a sensing transformer having a primary winding coupled to one of the buses by a switch so that the ripple on the d.c. bus is sensed. A periodic voltage is impressed across a secondary winding of an output inductor. A primary winding of the output inductor is connected between the output of the inverter and the load. The primary winding of the output inductor receives a first ripple component due to ripple on the d.c. bus and a second ripple component which opposes the first as a result of the periodic wave form in the secondary winding of the output inductor. The two ripple components substantially cancel one another and hence a low distortion power waveform is delivered to the load.
A more recent Glennon patent, U.S. Pat. No. 4,527,226, discloses a ripple reduction system in which set angles PWM for switching signals are stored. These set angles are intended to reduce ripple by taking into account the normalized d.c. bus voltage and the power factor of the load in selecting the angles. Glennon's circuit comprises an angle set look up table and selection logic for addressing the look up table. The angle set defining the inverter output waveform is selected in response to various operating conditions of the inverter.
Other prior inventions have addressed schemes for controlling current and voltage at the POR. Representative of such inventions is U.S. Pat. No. 4,595,976 to Parro, II, which discloses an inverter control system which is an enhancement of the Glennon inverter control. More specifically, the table look up is implemented as a plurality of memories, one for each phase, each of which is subdivided into a plurality of memory blocks which store a number of bytes. Memory address decoding logic addresses a particular memory block in each memory in accordance with a control signal representing the desired waveform to be generated at each phase output. Thus, the Parro, II inverter control accomplishes individual phase regulation of the inverter output.
U.S. Pat. No. 4,635,177 to Shekhawat et al. discloses a further refinement of the basic Glennon inverter control system. More specifically, the Shekhawat et al. control permits on-line generation of PWM patterns for a neutral point clamped PWM inverter. A microprocessor and memory are coupled to the generating circuitry for calculating switching points for the inverter switches during operation of the inverter. Timer modules are coupled to the microprocessor for developing switch points so that the switches are operated to reduce the distortion of the inverter output signal.
Also representative of the prior art are U.S. Pat. Nos. 4,357,655 to Beck, 4,757,434 to Kawabata et al., No. 4,763,059 to Espelage et al., and 4,800,478 to Takahashi. None of these, however, disclose a PWM selection algorithm which takes into account ripple on the d.c. link.
The wide range of link ripple and load variation encountered in certain applications require more patterns than can be economically stored if refined regulation is required. Current computing techniques do not allow for the iterative solution for patterns in real time.